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Freescale Semiconductor Data Sheet: Technical Data
Document Number: MC9S08QE32 Rev. 1, 6/2008
MC9S08QE32 Series
Covers: MC9S08QE32 and MC9S08QE16
Features
* 8-Bit HCS08 Central Processor Unit (CPU) - Up to 50.33 MHz HCS08 CPU at 3.6 V to 2.4 V, 40 MHz CPU at 2.4 V to 2.1 V and 20 MHz CPU at 2.1 V to 1.8 V across temperature range of -40C to 85C - HC08 instruction set with added BGND instruction - Support for up to 32 interrupt/reset sources * On-Chip Memory - Flash read/program/erase over full operating voltage and temperature - Random-access memory (RAM) - Security circuitry to prevent unauthorized access to RAM and flash contents * Power-Saving Modes - Two very low power stop modes - Reduced power wait mode - Peripheral clock enable register can disable clocks to unused modules, thereby reducing currents; allows clocks to remain enabled to specific peripherals in stop3 mode. - Very low power external oscillator that can be used in run, wait, and stop modes to provide accurate clock source to real time counter. - 6 s typical wake up time from stop3 mode * Clock Source Options - Oscillator (XOSCVLP) -- Loop-control Pierce oscillator; crystal or ceramic resonator range of 31.25 kHz to 38.4 kHz or 1 MHz to 16 MHz - Internal clock source (ICS) -- Internal clock source module containing a frequency-locked-loop (FLL) controlled by internal or external reference; precision trimming of internal reference allows 0.2% resolution and 2% deviation over temperature and voltage; supports CPU frequencies from 4kHz to 50.33 MHz. * System Protection - Watchdog computer operating properly (COP) reset with option to run from dedicated 1 kHz internal clock source or bus clock. - Low-voltage warning with interrupt. - Low-voltage detection with reset or interrupt - Selectable trip points. - Illegal opcode detection with reset - Illegal address detection with reset - Flash block protection * Development Support - Single-wire background debug interface
MC9S08QE32
48-QFN Case 1314 7 mm2 32-LQFP Case 873A 7 mm2 44-LQFP Case 824D
28-SOIC Case 751F
- Breakpoint capability to allow single breakpoint setting during in-circuit debugging (plus three breakpoints in on-chip debug module) - On-chip in-circuit emulator (ICE) debug module containing three comparators and nine trigger modes. Eight deep FIFO for storing change-of-flow addresses and event-only data. Debug module supports both tag and force breakpoints * Peripherals - ADC -- 10-channel, 12-bit resolution; 2.5 s conversion time; automatic compare function; 1.7 mV/C temperature sensor; internal bandgap reference channel; operation in stop3; fully functional from 3.6V to 1.8V - ACMPx -- Two analog comparators with selectable interrupt on rising, falling, or either edge of comparator output; compare option to fixed internal bandgap reference voltage; outputs can be optionally routed to TPM module; operation in stop3 - SCIx -- Two serial communications interface modules with optional 13-bit break. Full duplex non-return to zero (NRZ); LIN master extended break generation; LIN slave extended break detection; wake up on active edge. - SPI-- One serial peripheral interface; full-duplex or single-wire bidirectional; double-buffered transmit and receive; master or slave mode; MSB-first or LSB-first shifting - IIC -- One IIC; up to 100 kbps with maximum bus loading; multi-master operation; programmable slave address; interrupt driven byte-by-byte data transfer; supports broadcast mode and 10-bit addressing - TPMx -- One 6-channel (TPM3) and two 3-channel (TPM1 and TPM2); selectable input capture, output compare, or buffered edge- or center-aligned PWM on each channel; - RTC -- (Real-time counter) 8-bit modulus counter with binary or decimal based prescaler; external clock source for precise time base, time-of-day, calendar or task scheduling functions; free running on-chip low power oscillator (1 kHz) for cyclic wake-up without external components; runs in all MCU modes * Input/Output - 40 GPIOs, including 1 output-only pin and 1 input-only pin - 16 KBI interrupts with selectable polarity - Hysteresis and configurable pull up device on all input pins; Configurable slew rate and drive strength on all output pins. * Package Options - 48-pin QFN, 44-pin LQFP, 32-pin LQFP, 28-pin SOIC
This document contains information on a product under development. Freescale reserves the right to change or discontinue this product without notice. (c) Freescale Semiconductor, Inc., 2008. All rights reserved.
Table of Contents
1 2 3 MCU Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . 8 3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.2 Parameter Classification . . . . . . . . . . . . . . . . . . . 9 3.3 Absolute Maximum Ratings. . . . . . . . . . . . . . . . . 9 3.4 Thermal Characteristics. . . . . . . . . . . . . . . . . . . 10 3.5 ESD Protection and Latch-Up Immunity . . . . . . 11 3.6 DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . 12 3.7 Supply Current Characteristics . . . . . . . . . . . . . 15 3.8 External Oscillator (XOSCVLP) Characteristics 16 3.9 Internal Clock Source (ICS) Characteristics . . . 18 3.10 AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . 19 3.10.1Control Timing . . . . . . . . . . . . . . . . . . . . . 20 3.10.2TPM Module Timing . . . . . . . . . . . . . . . . 21 3.10.3SPI Timing . . . . . . . . . . . . . . . . . . . . . . . .21 3.11 Analog Comparator (ACMP) Electricals . . . . . . .25 3.12 ADC Characteristics . . . . . . . . . . . . . . . . . . . . . .25 3.13 Flash Specifications . . . . . . . . . . . . . . . . . . . . . .28 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . .29 Package Information . . . . . . . . . . . . . . . . . . . . . . . . . .29 5.1 Mechanical Drawings . . . . . . . . . . . . . . . . . . . . .29
4 5
Revision History
To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: http://freescale.com/ The following revision history table summarizes changes contained in this document.
Revision 1
Date 6/4/2008 Initial public released.
Description of Changes
Related Documentation
Find the most current versions of all documents at: http://www.freescale.com
Reference Manual (MC9S08QE32RM) Contains extensive product information including modes of operation, memory, resets and interrupts, register definition, port pins, CPU, and all module information.
MC9S08QE32 MCU Series Data Sheet, Rev. 1 2 Freescale Semiconductor
MCU Block Diagram
1
MCU Block Diagram
BKGD/MS
The block diagram, Figure 1, shows the structure of the MC9S08QE32 MCU.
PTA7/TPM2CH2/ADP9 PTA6/TPM1CH2/ADP8 PTA5/IRQ/TPM1CLK/RESET PTA4/ACMP1O/BKGD/MS PTA3/KBI1P3/SCL/ADP3 PTA2/KBI1P2/SDA/ADP2 PTA1/KBI1P1/TPM2CH0/ADP1/ACMP1- PTA0/KBI1P0/TPM1CH0/ADP0/ACMP1+ PTB7/SCL/EXTAL PTB6/SDA/XTAL PTB5/TPM1CH1/SS PORT B PTB4/TPM2CH1/MISO PTB3/KBI1P7/MOSI/ADP7 PTB2/KBI1P6/SPSCK/ADP6 PTB1/KBI1P5/TxD1/ADP5 PTB0/KBI1P4/RxD1/ADP4 PTC7/TxD2/ACMP2PTC6/RxD2/ACMP2+ PTC5/TPM3CH5/ACMP2O PORT C PTC4/TPM3CH4 PTC3/TPM3CH3 PTC2/TPM3CH2 6-CHANNEL TIMER/PWM MODULE (TPM3) ANALOG COMPARATOR (ACMP1) ANALOG COMPARATOR (ACMP2) 10-CHANNEL, 12-BIT ANALOG-TO-DIGITAL CONVERTER (ADC12) KEYBOARD INTERRUPT MODULE (KBI1) KEYBOARD INTERRUPT MODULE (KBI2) pins not available on 28-pin packages TPM3CLK TPM3CH5-TPM3CH0 ACMP1O ACMP1- ACMP1+ PTC1/TPM3CH1 PTC0/TPM3CH0 PTD7/KBI2P7 PTD6/KBI2P6 PTD5/KBI2P5 PORT D PTD4/KBI2P4 PTD3/KBI2P3 PTD2/KBI2P2 PTD1/KBI2P1 PTD0/KBI2P0 PTE7/TPM3CLK KBI1P7-KBI1P0 PORT E PTE6 PTE5 PTE4 PTE3/SS PTE2/MISO PTE1/MOSI PTE0/TPM2CLK/SPSCK pins not available on 28-pin or 32-pin packages pins not available on 28-pin, 32-pin, or 44-pin packages Notes: When PTA5 is configured as RESET, pin becomes bi-directional with output being open-drain drive containing an internal pull-up device. When PTA4 is configured as BKGD, pin becomes bi-directional. For the 28-pin packages: VSSAD/VREFL and VDDAD/VREFH are double bonded to VSS and VDD respectively. The 48-pin package is the only package with the option of having the SPI pins (SS, MISO, MOSI, and SPSCK) available on PTE3-0 pins.
HCS08 CORE CPU BDC
DEBUG MODULE (DBG) PORT A
SCL
REAL-TIME COUNTER (RTC) IIC MODULE (IIC) SDA RxD1 TxD1 RxD2 TxD2 SS MISO MOSI SPSCK TPM1CLK TPM1CH2-TPM1CH0 TPM2CLK TPM2CH2-TPM2CH0
HCS08 SYSTEM CONTROL RESETS AND INTERRUPTS MODES OF OPERATION POWER MANAGEMENT COP IRQ LVD
IRQ
SERIAL COMMUNICATIONS INTERFACE MODULE(SCI1) SERIAL COMMUNICATIONS INTERFACE MODULE(SCI2) SERIAL PERIPHERAL INTERFACE MODULE(SPI) 3-CHANNEL TIMER/PWM MODULE (TPM1) 3-CHANNEL TIMER/PWM MODULE (TPM2) EXTAL XTAL VSSAD VDDAD VSSAD VDDAD
USER FLASH (MC9S08QE32 = 32768 BYTES) (MC9S08QE16 = 16384 BYTES) USER RAM (MC9S08QE32 = 2048 BYTES) (MC9S08QE16 = 1024 BYTES)
50.33 MHz INTERNAL CLOCK SOURCE (ICS) LOW-POWER OSCILLATOR 31.25 kHz to 38.4 kHz 1 MHz to 16 MHz (XOSCVLP) VSS VDD VOLTAGE REGULATOR
VSSAD/VREFL VDDAD/VREFH VREFL VREFH
ACMP2O ACMP2- ACMP2+
ADP9-ADP0
KBI2P7-KBI2P0
Figure 1. MC9S08QE32 Series Block Diagram
MC9S08QE32 MCU Series Data Sheet, Rev. 1 Freescale Semiconductor 3
Pin Assignments
2
Pin Assignments
38 PTA0/KBI1P0/TPM1CH0/ADP0/ACMP1+ PTB3/KBI1P7/MOSI/ADP7 23 PTA1/KBI1P1/TPM2CH0/AD 37 PTA1/KBI1P1/TPM2CH0/ADP1/ACMP1- PTB2/KBI1P6/SPSCK/ADP6 24
This section shows the pin assignments for the MC9S08QE32 Series devices.
47 PTA5/IRQ/TPM1CLK/RESET
45 PTC5/TPM3CH5/ACMP2O
48 PTA4/ACMP1O/BKGD/MS
44 PTE0/TPM2CLK/SPSCK
40 PTC6/RxD2/ACMP2+
39 PTC7/TxD2/ACMP2-
46 PTC4/TPM3CH4
43 PTE1/MOSI
42 PTE2/MISO
41 PTE3/SS
PTD1/KBI2P1 1 PTD0/KBI2P0 2 PTE7/TPM3CLK 3 VDD 4 VDDAD 5 VREFH 6 VREFL 7 VSSAD 8 VSS 9 PTB7/SCL/EXTAL 10 PTB6/SDA/XTAL 11 PTE6 12 PTE5 13 PTB5/TPM1CH1/SS 14 PTB4/TPM2CH1/MISO 15 PTC3/TPM3CH3 16 PTC2/TPM3CH2 17 PTD7/KBI2P7 18 PTD6/KBI2P6 19 PTD5/KBI2P5 20 PTC1/TPM3CH1 21 PTC0/TPM3CH0 22
36 PTA2/KBI1P2/SDA/ADP2 35 PTA3/KBI1P3/SCL/ADP3 34 PTD2/KBI2P2 33 PTD3/KBI2P3 32 PTD4/KBI2P4 31 VSS 30 VDD 29 PTE4 28 PTA6/TPM1CH2/ADP8 27 PTA7/TPM2CH2/ADP9 26 PTB0/KBI1P4/RxD1/ADP4 25 PTB1/KBI1P5/TxD1/ADP5
Pins in bold are lost in the next lower pin count package.
Figure 2-2. 48-Pin QFN
MC9S08QE32 MCU Series Data Sheet, Rev. 1 4 Freescale Semiconductor
Pin Assignments
PTA0/KBI1P0/TPM1CH0/ADP0/ACMP 35 PTA1/KBI1P1/TPM2CH0/ADP1/ACMP 34 33 32 31 30 29 28 27 26 25 24 13 14 15 16 17 18 19 20 21 22 23
PTA5/IRQ/TPM1CLK/RESET
PTC5/TPM3CH5/ACMP2O
PTA4/ACMP1O/BKGD/MS
PTC6/RxD2/ACMP2+ 37
43
42
41
44
40
39
38
PTD1/KBI2P1 PTD0/KBI2P0 PTE7/TPM3CLK VDD VDDAD VREFH VREFL VSSAD VSS PTB7/SCL/EXTAL PTB6/SDA/XTAL 11
1 2 3 4 5 6 7 8 9 10
36
PTC7/TxD2/ACMP2-
PTC4/TPM3CH4
PTE0/TPM2CLK
PTE1
PTE2
PTA2/KBI1P2/SDA/ADP2 PTA3/KBI1P3/SCL/ADP3 PTD2/KBI2P2 PTD3/KBI2P3 PTD4/KBI2P4 VSS VDD PTA6/TPM1CH2/ADP8 PTA7/TPM2CH2/ADP9 PTB0/KBI1P4/RxD1/ADP4 PTB1/KBI1P5/TxD1/ADP5
12
PTB5/TPM1CH1/SS
PTB4/TPM2CH1/MISO
PTC3/TPM3CH3
PTC2/TPM3CH2
PTD7/KBI2P7
PTC1/TPM3CH1
PTC0/TPM3CH0
Pins in bold are lost in the next lower pin count package.
Figure 2-3. 44-pin LQFP
MC9S08QE32 MCU Series Data Sheet, Rev. 1 Freescale Semiconductor 5
PTB2/KBI1P6/SPSCK/ADP6
PTD6/KBI2P6
PTB3/KBI1P7/MOSI/ADP7
PTD5/KBI2P5
Pin Assignments
PTA0/KBI1P0/TPM1CH0/ADP0/ACMP1+ 26 PTA1/KBI1P1/TPM2CH0/ADP1/ACMP1- 25 24 23 22 21 20 19 18 17 9 PTB5/TPM1CH1/SS 10 PTB4/TPM2CH1/MISO 11 PTC3/TPM3CH3 12 PTC2/TPM3CH2 13 PTC1/TPM3CH1 14 PTC0/TPM3CH0 15 PTB3/KBI1P7/MOSI/ADP7 16 PTB2/KBI1P6/SPSCK/ADP6 PTA2/KBI1P2/SDA/ADP2 PTA3/KBI1P3/SCL/ADP3 PTD2/KBI2P2 PTD3/KBI2P3 PTA6/TPM1CH2/ADP8 PTA7/TPM2CH2/ADP9 PTB0/KBIP4/RxD1/ADP4 PTB1/KBIP5/TxD1/ADP5
PTA5/IRQ/TPM1CLK/RESET
PTA4/ACMP1O/BKGD/MS
PTC5/TPM3CH5/ACMP2O
PTC6/RxD2/ACMP2+ 28
PTD1/KBI2P1 PTD0/KBI2P0 VDD VDDAD/VREFH VSSAD/VREFL VSS PTB7/SCL/EXTAL PTB6/SDA/XTAL
1 2 3 4 5 6 7 8
32
31
PTC4/TPM3CH4
30
29
Pins in bold are lost in the next lower pin count package.
Figure 2-4. 32-LQFP
MC9S08QE32 MCU Series Data Sheet, Rev. 1 6 Freescale Semiconductor
PTC7/TxD2/ACMP227
Pin Assignments
PTC5/TPM3CH5/ACMP2O PTC4/TPM3CH4 PTA5/IRQ/TPM1CLK/RESET PTA4/ACMP1O/BKGD/MS VDD VDDAD/VREFH VSSAD/VREFL VSS PTB7/SCL/EXTAL PTB6/SDA/XTAL PTB5/TPM1CH1/SS PTB4/TPM2CH1/MISO PTC3/TPM3CH3 PTC2/TPM3CH2
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
PTC6/RxD2/ACMP2+ PTC7/TxD2/ACMP2PTA0/KBI1P0/TPM1CH0/ADP0/ACMP1+ PTA1/KBI1P1/TPM2CH0/ADP1/ACMP1PTA2/KBI1P2/SDA/ADP2 PTA3/KBI1P3/SCL/ADP3 PTA6/TPM1CH2/ADP8 PTA7/TPM2CH2/ADP9 PTB0/KBI1P4/RxD1/ADP4 PTB1/KBI1P5/TxD1/ADP5 PTB2/KBI1P6/SPSCK/ADP6 PTB3/KBI1P7/MOSI/ADP7 PTC0/TPM3CH0 PTC1/TPM3CH1
Figure 2-5. 28-pin SOIC Table 2-1. MC9S08QE32 Series Pin Assignment by Package and Pin Sharing Priority
Pin Number 48 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 44 1 2 3 4 5 6 7 8 9 10 11 -- -- 12 13 14 15 16 6 7 8 -- -- 9 10 11 12 -- 8 9 10 -- -- 11 12 13 14 -- PTB7 PTB6 PTE6 PTE5 PTB5 PTB4 PTC3 PTC2 PTD7 TPM1CH1 SS2 TPM2CH1 MISO2 TPM3CH3 TPM3CH2 KBI2P7 SCL1 SDA1 5 7 32 1 2 -- 3 4 28 -- -- -- 5 6 Port Pin PTD1 PTD0 PTE7 <-- Lowest Alt 1 KBI2P1 KBI2P0 TPM3CLK VDD VDDAD VREFH VREFL VSSAD VSS EXTAL XTAL Priority Alt 2 --> Highest Alt 3 Alt 4
MC9S08QE32 MCU Series Data Sheet, Rev. 1 Freescale Semiconductor 7
Electrical Characteristics
Table 2-1. MC9S08QE32 Series Pin Assignment by Package and Pin Sharing Priority (continued)
Pin Number 48 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48
1
<-- Lowest 28 -- -- 15 16 17 18 19 20 21 22 -- -- -- -- -- -- 23 24 25 26 27 28 -- -- -- -- 1 2 3 4 PTD4 PTD3 PTD2 PTA3 PTA2 PTA1 PTA0 PTC7 PTC6 PTE3 PTE2 PTE1 PTE0 PTC5 PTC4 PTA5 PTA4 KBI2P4 KBI2P3 KBI2P2 KBI1P3 KBI1P2 KBI1P1 KBI1P0 TxD2 RxD2 SS2 MISO2 MOSI2 Port Pin PTD6 PTD5 PTC1 PTC0 PTB3 PTB2 PTB1 PTB0 PTA7 PTA6 PTE4 Alt 1 KBI2P6 KBI2P5 TPM3CH1 TPM3CH0 KBI1P7 KBI1P6 KBI1P5 KBI1P4 TPM2CH2 TPM1CH2
Priority Alt 2
--> Highest Alt 3 Alt 4
44 17 18 19 20 21 22 23 24 25 26 -- 27 28 29 30 31 32 33 34 35 36 37 -- 38 39 40 41 42 43 44
32 -- -- 13 14 15 16 17 18 19 20 -- -- -- -- 21 22 23 24 25 26 27 28 -- -- -- -- 29 30 31 32
MOSI2 SPSCK2 TxD1 RxD1
ADP7 ADP6 ADP5 ADP4 ADP9 ADP8 VDD VSS
SCL1 SDA1 TPM2CH0 ADP13 TPM1CH0 ADP03
ADP3 ADP2 ACMP1-3 ACMP1+3 ACMP2ACMP2+
TPM2CLK SPSCK2 TPM3CH5 TPM3CH4 IRQ ACMP1O TPM1CLK RESET BKGD MS ACMP2O
IIC pins, SCL and SDA can be repositioned using IICPS in SOPT2; default reset locations are PTA3 and PTA2. 2 SPI pins (SS, MISO, MOSI, and SPSCK) can be repositioned using SPIPS in SOPT2. Default locations are PTB5, PTB4,PTB3, and PTB2. 3 If ADC and ACMP1 are enabled, both modules will have access to the pin.
3
3.1
Electrical Characteristics
Introduction
This section contains electrical and timing specifications for the MC9S08QE32 Series of microcontrollers available at the time of publication.
MC9S08QE32 MCU Series Data Sheet, Rev. 1 8 Freescale Semiconductor
Electrical Characteristics
3.2
Parameter Classification
Table 2. Parameter Classifications P C
Those parameters are guaranteed during production testing on each individual device. Those parameters are achieved by the design characterization by measuring a statistically relevant sample size across process variations. Those parameters are achieved by design characterization on a small sample size from typical devices under typical conditions unless otherwise noted. All values shown in the typical column are within this category. Those parameters are derived mainly from simulations.
The electrical parameters shown in this supplement are guaranteed by various methods. To give the customer a better understanding the following classification is used and the parameters are tagged accordingly in the tables where appropriate:
T D
NOTE The classification is shown in the column labeled "C" in the parameter tables where appropriate.
3.3
Absolute Maximum Ratings
Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. Stress beyond the limits specified in Table 3 may affect device reliability or cause permanent damage to the device. For functional operating conditions, refer to the remaining tables in this section. This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (for instance, either VSS or VDD) or the programmable pull-up resistor associated with the pin is enabled. Table 3. Absolute Maximum Ratings
Rating Supply voltage Maximum current into VDD Digital input voltage Instantaneous maximum current Single pin limit (applies to all port pins)1, 2, 3 Storage temperature range
1
Symbol VDD IDD VIn ID Tstg
Value -0.3 to +3.8 120 -0.3 to VDD + 0.3 25 -55 to 150
Unit V mA V mA C
Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate resistance values for positive (VDD) and negative (VSS) clamp voltages, then use the larger of the two resistance values. 2 All functional non-supply pins, except for PTA5 are internally clamped to V SS and VDD.
MC9S08QE32 MCU Series Data Sheet, Rev. 1 Freescale Semiconductor 9
Electrical Characteristics
3
Power supply must maintain regulation within operating VDD range during instantaneous and operating maximum current conditions. If positive injection current (VIn > VDD) is greater than IDD, the injection current may flow out of VDD and could result in external power supply going out of regulation. Ensure external VDD load will shunt current greater than maximum injection current. This will be the greatest risk when the MCU is not consuming power. Examples are: if no system clock is present, or if the clock rate is very low (which would reduce overall power consumption).
3.4
Thermal Characteristics
This section provides information about operating temperature range, power dissipation, and package thermal resistance. Power dissipation on I/O pins is usually small compared to the power dissipation in on-chip logic and voltage regulator circuits, and it is user-determined rather than being controlled by the MCU design. To take PI/O into account in power calculations, determine the difference between actual pin voltage and VSS or VDD and multiply by the pin current for each I/O pin. Except in cases of unusually high pin current (heavy loads), the difference between pin voltage and VSS or VDD will be very small. Table 4. Thermal Characteristics
Rating Operating temperature range (packaged) Maximum junction temperature Thermal resistance Single-layer board 48-pin QFN 44-pin LQFP 32-pin LQFP 28-pin SOIC Thermal resistance Four-layer board 48-pin QFN 44-pin LQFP 32-pin LQFP 28-pin SOIC JA 26 46 54 42 C/W JA 81 68 66 57 C/W Symbol TA TJM Value TL to TH -40 to 85 95 Unit C C
The average chip-junction temperature (TJ) in C can be obtained from: TJ = TA + (PD x JA) where: TA = Ambient temperature, C JA = Package thermal resistance, junction-to-ambient, C/W PD = Pint + PI/O Pint = IDD x VDD, Watts -- chip internal power PI/O = Power dissipation on input and output pins -- user determined For most applications, PI/O << Pint and can be neglected. An approximate relationship between PD and TJ (if PI/O is neglected) is: Eqn. 1
MC9S08QE32 MCU Series Data Sheet, Rev. 1 10 Freescale Semiconductor
Electrical Characteristics
PD = K / (TJ + 273C) Solving Equation 1 and Equation 2 for K gives: K = PD x (TA + 273C) + JA x (PD)2
Eqn. 2
Eqn. 3
where K is a constant pertaining to the particular part. K can be determined from equation 3 by measuring PD (at equilibrium) for a known TA. Using this value of K, the values of PD and TJ can be obtained by solving Equation 1 and Equation 2 iteratively for any value of TA.
3.5
ESD Protection and Latch-Up Immunity
Although damage from electrostatic discharge (ESD) is much less common on these devices than on early CMOS circuits, normal handling precautions must be used to avoid exposure to static discharge. Qualification tests are performed to ensure that these devices can withstand exposure to reasonable levels of static without suffering any permanent damage. All ESD testing is in conformity with AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits. During the device qualification ESD stresses were performed for the human body model (HBM), the machine model (MM) and the charge device model (CDM). A device is defined as a failure if after exposure to ESD pulses the device no longer meets the device specification. Complete DC parametric and functional testing is performed per the applicable device specification at room temperature followed by hot temperature, unless specified otherwise in the device specification. Table 5. ESD and Latch-up Test Conditions Model
Human Body
Description
Series resistance Storage capacitance Number of pulses per pin
Symbol
R1 C -- R1 C --
Value
1500 100 3 0 200 3 -2.5 7.5
Unit
pF
Machine
Series resistance Storage capacitance Number of pulses per pin
pF
Latch-up
Minimum input voltage limit Maximum input voltage limit
V V
Table 6. ESD and Latch-Up Protection Characteristics No.
1 2 3 4
1
Rating1
Human body model (HBM) Machine model (MM) Charge device model (CDM) Latch-up current at TA = 85C
Symbol
VHBM VMM VCDM ILAT
Min
2000 200 500 100
Max
-- -- -- --
Unit
V V V mA
Parameter is achieved by design characterization on a small sample size from typical devices under typical conditions unless otherwise noted.
MC9S08QE32 MCU Series Data Sheet, Rev. 1 Freescale Semiconductor 11
Electrical Characteristics
3.6
DC Characteristics
Table 7. DC Characteristics
This section includes information about power supply requirements and I/O pin characteristics.
Num C 1 C 2 P T C 3 Output high D current C 4 P Output low voltage T C 5 6 7 8 D Output low current
Characteristic Operating Voltage Output high voltage2 All I/O pins, low-drive strength All I/O pins, high-drive strength Max total IOH for all ports All I/O pins, low-drive strength All I/O pins, high-drive strength Max total IOL for all ports all digital inputs all digital inputs all digital inputs all input only pins (Per pin)
Symbol
Condition
Min 1.8
Typical1
Max 3.6
Unit V
1.8 V, ILoad = -2 mA VOH
VDD - 0.5
-- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- 100 0.5 0.5 0.5 0.5 100 -- -- 0.35 x VDD 0.30 x VDD -- mV V mA V mA V
2.7 V, ILoad = -10 mA VDD - 0.5 2.3 V, ILoad = -6 mA VDD - 0.5 1.8V, ILoad = -3 mA VDD - 0.5 -- 1.8 V, ILoad = 2 mA -- -- -- -- -- VDD > 2.3 V VDD 1.8 V VDD > 2.7 V VDD 1.8 V 0.70 x VDD 0.85 x VDD -- -- 0.06 x VDD VIn = VDD or VSS --
IOHT
VOL
2.7 V, ILoad = 10 mA 2.3 V, ILoad = 6 mA 1.8 V, ILoad = 3 mA
IOLT VIH VIL Vhys |IIn|
P Input high C voltage P Input low C voltage C Input hysteresis
9
Input P leakage current Hi-Z (off-state) P leakage current Pullup, P Pulldown resistors DC injection D current 3, 4,
5
5
1000
nA
10
all input/output (per pin)
|IOZ|
VIn = VDD or VSS
--
5
1000
nA
11
all digital inputs, when enabled Single pin limit Total MCU limit, includes sum of all stressed pins
RPU, RPD
17.5 -0.2
-- -- -- -- 0.6 1.4 -- 2.16 2.21
52.5 0.2 5 8 1.0 2.0 -- 2.22 2.27
k mA mA pF V V s V
12 13 14 15 16 17
IIC CIn VRAM VPOR tPOR VLVDH
VIN < VSS, VIN > VDD
-5 -- -- 0.9 10
C Input Capacitance, all pins C RAM retention voltage C POR re-arm voltage D POR re-arm time Low-voltage detection threshold-- P high range
6
VDD falling VDD rising
2.11 2.16
MC9S08QE32 MCU Series Data Sheet, Rev. 1 12 Freescale Semiconductor
Electrical Characteristics
Table 7. DC Characteristics (continued)
Num C 18 19 20 21 22
1 2 3 4 5
Characteristic Low-voltage detection threshold-- low range Low-voltage warning threshold-- high range Low-voltage warning threshold-- low range Low-voltage inhibit reset/recover hysteresis
Symbol VLVDL VLVWH VLVWL Vhys VBG
Condition VDD falling VDD rising VDD falling VDD rising VDD falling VDD rising
Min 1.80 1.88 2.36 2.36 2.11 2.16 -- 1.15
Typical1 1.82 1.90 2.46 2.46 2.16 2.21 80 1.17
Max 1.91 1.99 2.56 2.56 2.22 2.27 -- 1.18
Unit V V V mV V
P P P C
P Bandgap Voltage Reference7
6 7
Typical values are measured at 25C. Characterized, not tested As the supply voltage rises, the LVD circuit will hold the MCU in reset until the supply has risen above VLVDL. All functional non-supply pins, except for PTA5 are internally clamped to VSS and VDD. Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate resistance values for positive and negative clamp voltages, then use the larger of the two values. Power supply must maintain regulation within operating VDD range during instantaneous and operating maximum current conditions. If positive injection current (VIn > VDD) is greater than IDD, the injection current may flow out of VDD and could result in external power supply going out of regulation. Ensure external VDD load will shunt current greater than maximum injection current. This will be the greatest risk when the MCU is not consuming power. Examples are: if no system clock is present, or if clock rate is very low (which would reduce overall power consumption). Maximum is highest voltage that POR is guaranteed. Factory trimmed at VDD = 3.0 V, Temp = 25C
PULL-UP RESISTOR (k)
PULLDOWN RESISTANCE (k)
40 35 30 25 20
PULLUP RESISTOR TYPICALS
85C 25C -40C
40 35 30 25 20
PULLDOWN RESISTOR TYPICALS
85C 25C -40C
1.8
2
2.2
2.4
2.6 2.8 VDD (V)
3
3.2
3.4
3.6
1.8
2.3
2.8 VDD (V)
3.3
3.6
Figure 6. Pullup and Pulldown Typical Resistor Values (VDD = 3.0 V)
MC9S08QE32 MCU Series Data Sheet, Rev. 1 Freescale Semiconductor 13
Electrical Characteristics
1.2 1 0.8 VOL (V) 0.6 0.4 0.2 0 0
TYPICAL VOL VS IOL AT VDD = 3.0 V
85C 25C -40C
0.2 0.15 VOL (V) 0.1 0.05 0
TYPICAL VOL VS VDD
85C, IOL = 2 mA 25C, IOL = 2 mA -40C, IOL = 2 mA
5
10 IOL (mA)
15
20
1
2
VDD (V)
3
4
Figure 7. Typical Low-Side Driver (Sink) Characteristics -- Low Drive (PTxDSn = 0)
TYPICAL VOL VS VDD 0.4 0.3 VOL (V) 0.2 0.1 0 0 10 IOL (mA) 20 30 1 2 VDD (V) IOL = 3 mA 3 4 IOL = 6 mA
85C 25C -40C
1 0.8 0.6 VOL (V) 0.4 0.2 0
TYPICAL VOL VS IOL AT VDD = 3.0 V
85C 25C -40C
IOL = 10 mA
Figure 8. Typical Low-Side Driver (Sink) Characteristics -- High Drive (PTxDSn = 1)
TYPICAL VDD - VOH VS IOH AT VDD = 3.0 V
85C 25C -40C
1.2 1 VDD - VOH (V) 0.8 0.6 0.4 0.2 0 0
0.25 0.2 VDD - VOH (V) 0.15 0.1 0.05 0
TYPICAL VDD - VOH VS VDD AT SPEC IOH
85C, IOH = 2 mA 25C, IOH = 2 mA -40C, IOH = 2 mA
-5
-10 IOH (mA))
-15
-20
1
2
VDD (V)
3
4
Figure 9. Typical High-Side (Source) Characteristics -- Low Drive (PTxDSn = 0)
MC9S08QE32 MCU Series Data Sheet, Rev. 1 14 Freescale Semiconductor
Electrical Characteristics
TYPICAL VDD - VOH VS VDD AT SPEC IOH
85C 25C -40C
0.4
0.8 TYPICAL VDD - VOH VS IOH AT VDD = 3.0 V
VDD - VOH (V)
0.6 0.4 0.2 0 0
VDD - VOH (V)
85C 25C -40C
0.3 0.2 0.1 0 1
IOH = -10 mA IOH = -6 mA IOH = -3 mA 2 VDD (V) 3 4
-5
-10
-15 -20 IOH (mA)
-25
-30
Figure 10. Typical High-Side (Source) Characteristics -- High Drive (PTxDSn = 1)
3.7
Supply Current Characteristics
Table 8. Supply Current Characteristics
This section includes information about power supply current in various operating modes.
Num
C P T
Parameter Run supply current FEI mode, all modules on
Symbol
Bus Freq 25.165 MHz 20 MHz
VDD (V)
Typical1 17.3 13.75
Max 20 --
Unit
Temp (C)
1 T T C T 2 T T T 3 T T 4 T C T 5 T T P 6 C P 7 C Stop3 mode supply current No clocks active Stop2 mode supply current Run supply current LPRS=1, all modules off, running from RAM Wait mode supply current FEI mode, all modules off Run supply current LPRS=0, all modules off Run supply current LPRS=1, all modules off, running from Flash Run supply current FEI mode, all modules off
RIDD
3 8 MHz 1 MHz 25.165 MHz 20 MHz 5.59 1.03 11.5 9.5 3 8 MHz 1 MHz 16 kHz FBILP 4.6 1.0 152 3 16 kHz FBELP 115 21.9 -- -- -- -- -- -- -- 12.3 --
mA
-40 to 85
RIDD
mA
-40 to 85
RIDD
A
-40 to 85
RIDD
16 kHz FBELP
3 7.3 --
A
-40 to 85
25.165 MHz 20 MHz WIDD 3 8 MHz 1 MHz n/a S2IDD S3IDD n/a n/a n/a 3 2 3 2
5740 4570 2000 730 0.35 0.25 0.45 0.35
6000 -- -- -- 7.5 6.5 15 13.2 A A -40 to 85 -40 to 85 -40 to 85 -40 to 85 A --40 to 85
MC9S08QE32 MCU Series Data Sheet, Rev. 1 Freescale Semiconductor 15
Electrical Characteristics
Table 8. Supply Current Characteristics (continued)
Num 8 9 10 11 12 13 14 15
1
C T T T T T T T T
Parameter EREFSTEN=1 IREFSTEN=1 TPM PWM SCI, SPI, or IIC Low power mode adders: RTC using LPO RTC using ICSERCLK LVD ACMP
Symbol
Bus Freq 32 kHz 32 kHz 100 Hz 300 bps 1 kHz 32 kHz n/a n/a
VDD (V)
Typical1 500 70
Max -- -- -- -- -- -- -- --
Unit nA A A A nA A A A
Temp (C)
12 15
3
200 1 100 20
-40 to 85
Data in Typical column was characterized at 3.0 V, 25C or is typical recommended value.
3.8
External Oscillator (XOSCVLP) Characteristics
Reference Figure 11 and Figure 12 for crystal or resonator circuits.
MC9S08QE32 MCU Series Data Sheet, Rev. 1 16 Freescale Semiconductor
Electrical Characteristics
Table 9. XOSC and ICS Specifications (Temperature Range = -40 to 85C Ambient)
Num C Characteristic Symbol flo fhi fhi Min Typical1 Max Unit
1
Oscillator crystal or resonator (EREFS = 1, ERCLKEN = 1) Low range (RANGE = 0) C High range (RANGE = 1), high gain (HGO = 1) High range (RANGE = 1), low power (HGO = 0) Load capacitors Low range (RANGE=0), low power (HGO=0) D Other oscillator settings Feedback resistor Low range, low power (RANGE=0, HGO=0)2 D Low range, High Gain (RANGE=0, HGO=1) High range (RANGE=1, HGO=X) Series resistor -- Low range, low power (RANGE = 0, HGO = 0)2 Low range, high gain (RANGE = 0, HGO = 1) High range, low power (RANGE = 1, HGO = 0) D High range, high gain (RANGE = 1, HGO = 1) 8 MHz 4 MHz 1 MHz Crystal start-up time 4 Low range, low power Low range, high power C High range, low power High range, high power Square wave input clock frequency (EREFS = 0, ERCLKEN = 1) FEE mode FBE or FBELP mode
32 1 1
-- -- --
38.4 16 8
kHz MHz MHz
2
C1,C2
See Note 2 See Note 3
3
RF
-- -- -- -- -- -- -- -- --
-- 10 1 -- 100 0 0 0 0 200 400 5 15
-- -- -- -- -- -- 0 10 20 -- -- -- --
M
4
RS
k
t CSTL t CSTH
5
-- -- -- --
ms
6
1 2
D
fextal
0.03125 0
-- --
40 40
MHz MHz
Data in Typical column is characterized at 3.0 V, 25C or is typical recommended value. Load capacitors (C1,C2), feedback resistor (RF) and series resistor (RS) are incorporated internally when RANGE=HGO=0. 3 See crystal or resonator manufacturer's recommendation. 4 Proper PC board layout procedures must be followed to achieve specifications.
MC9S08QE32 MCU Series Data Sheet, Rev. 1 Freescale Semiconductor 17
Electrical Characteristics
XOSCVLP EXTAL XTAL RS
RF
C1
Crystal or Resonator C2
Figure 11. Typical Crystal or Resonator Circuit: High Range and Low Range/High Gain
XOSCVLP EXTAL XTAL
Crystal or Resonator
Figure 12. Typical Crystal or Resonator Circuit: Low Range/Low Power
3.9
Num 1 2 3 C
Internal Clock Source (ICS) Characteristics
Table 10. ICS Frequency Specifications (Temperature Range = -40 to 85C Ambient)
Characteristic Symbol fint_ut fint_t tIRST Low range (DFR=00) DCO output frequency trimmed2 DCO output frequency2 Reference = 32768 Hz and DMX32 = 1 Mid range (DFR=01) High range (DFR=10) Low range (DFR=00) Mid range (DFR=01) High range (DFR=10) fdco_res_t fdco_res_t fdco_DMX32 fdco_u Min -- 31.25 -- 16 32 48 -- -- -- -- -- Typical1 32.768 -- 60 -- -- -- 19.92 39.85 59.77 0.1 0.2 Max -- 39.06 100 20 40 60 -- -- -- 0.2 0.4 %fdco %fdco MHz MHz Unit kHz kHz s
C Average internal reference frequency - untrimmed P T P Average internal reference frequency - trimmed Internal reference start-up time
4
P P P
5
P P
6 7
C C
Resolution of trimmed DCO output frequency at fixed voltage and temperature (using FTRIM) Resolution of trimmed DCO output frequency at fixed voltage and temperature (not using FTRIM)
MC9S08QE32 MCU Series Data Sheet, Rev. 1 18 Freescale Semiconductor
Electrical Characteristics
Table 10. ICS Frequency Specifications (Temperature Range = -40 to 85C Ambient) (continued)
Num 8 9 10 11
1 2
C C C
Characteristic Total deviation of trimmed DCO output frequency over voltage and temperature Total deviation of trimmed DCO output frequency over fixed voltage and temperature range of 0C to 70 C
Symbol fdco_t fdco_t tAcquire CJitter
Min -- -- -- --
Typical1 + 0.5 -1.0 0.5 -- 0.02
Max 2 1 1 0.2
Unit %fdco %fdco ms %fdco
C FLL acquisition time 3 C Long term jitter of DCO output clock (averaged over 2-ms interval) 4
Data in Typical column is characterized at 3.0 V, 25C or is typical recommended value. The resulting bus clock frequency should not exceed the maximum specified bus clock frequency of the device. 3 This specification applies to any time the FLL reference source or reference divider is changed, trim value changed or changing from FLL disabled (FBELP, FBILP) to FLL enabled (FEI, FEE, FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running. 4 Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum f Bus. Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise injected into the FLL circuitry via VDD and VSS and variation in crystal oscillator frequency increase the CJitter percentage for a given interval.
3.10
AC Characteristics
0.40%
This section describes timing characteristics for each peripheral system.
0.20%
0.00%
-0.20%
DEVIATION
-0.40%
-0.60%
-0.80% -60 -40 -20 0 20 40 60 80 100 120 140
TEMPERATURE
MC9S08QE32 MCU Series Data Sheet, Rev. 1 Freescale Semiconductor 19
Electrical Characteristics
3.10.1
Control Timing
Table 11. Control Timing
Num
C
Rating Bus frequency (tcyc = 1/fBus)
Symbol
Min
Typical1
Max
Unit
1
D
VDD 2.1V 2.1 2.4Vs Internal low power oscillator period External reset pulse width2 Reset low drive BKGD/MS setup time after issuing background debug force reset to enter user or BDM modes BKGD/MS hold time after issuing background debug force reset to enter user or BDM modes 3 IRQ pulse width Asynchronous path2 Synchronous path4 Keyboard interrupt pulse width Asynchronous path2 Synchronous path5 Port rise and fall time -- Low output drive (PTxDS = 0) (load = 50 pF)5 Slew rate control disabled (PTxSE = 0) Slew rate control enabled (PTxSE = 1) Port rise and fall time -- High output drive (PTxDS = 1) (load = 50 pF) Slew rate control disabled (PTxSE = 0) Slew rate control enabled (PTxSE = 1)
fBus
DC
-- --
10 20 25.165 1300 -- -- -- --
MHz
2 3 4 5 6
D D D D D
tLPO textrst trstdrv tMSSU tMSH
700 100 34 x tcyc 500 100
-- -- -- -- --
s ns ns ns s
7
D
tILIH, tIHIL
100 1.5 x tcyc 100 1.5 x tcyc
-- -- -- --
-- -- -- --
ns
8
D
tILIH, tIHIL
ns
tRise, tFall
-- --
8 31
-- --
ns
9
C
tRise, tFall
-- -- --
7 24 4
-- -- --
ns
10
1 2
C
Voltage regulator recovery time
tVRR
s
Typical values are based on characterization data at VDD = 3.0V, 25C unless otherwise stated. This is the shortest pulse that is guaranteed to be recognized as a reset pin request. Shorter pulses are not guaranteed to override reset requests from internal sources. 3 To enter BDM mode following a POR, BKGD/MS must be held low during the power-up and for a hold time of t MSH after VDD rises above VLVD. 4 This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or may not be recognized. In stop mode, the synchronizer is bypassed so shorter pulses can be recognized in that case. 5 Timing is shown with respect to 20% V DD and 80% VDD levels. Temperature range -40C to 85C.
textrst RESET PIN
Figure 13. Reset Timing
MC9S08QE32 MCU Series Data Sheet, Rev. 1 20 Freescale Semiconductor
Electrical Characteristics
tIHIL KBIPx
IRQ/KBIPx tILIH
Figure 14. IRQ/KBIPx Timing
3.10.2
TPM Module Timing
Synchronizer circuits determine the shortest input pulses that can be recognized or the fastest clock that can be used as the optional external source to the timer counter. These synchronizers operate from the current bus rate clock. Table 12. TPM Input Timing
No. 1 2 3 4 5 C D D D D D Function External clock frequency External clock period External clock high time External clock low time Input capture pulse width Symbol fTCLK tTCLK tclkh tclkl tICPW Min 0 4 1.5 1.5 1.5 Max fBus/4 -- -- -- -- Unit Hz tcyc tcyc tcyc tcyc
tTCLK tclkh
TCLK tclkl
Figure 15. Timer External Clock
tICPW TPMCHn
TPMCHn tICPW
Figure 16. Timer Input Capture Pulse
3.10.3
SPI Timing
Table 13 and Figure 17 through Figure 20 describe the timing requirements for the SPI system.
MC9S08QE32 MCU Series Data Sheet, Rev. 1 Freescale Semiconductor 21
Electrical Characteristics
Table 13. SPI Timing
No. -- C D Function Operating frequency Master Slave SPSCK period Master Slave Enable lead time Master Slave Enable lag time Master Slave Clock (SPSCK) high or low time Master Slave Data setup time (inputs) Master Slave Data hold time (inputs) Master Slave Slave access time Slave MISO disable time Data valid (after SPSCK edge) Master Slave Data hold time (outputs) Master Slave Rise time Input Output Fall time Input Output Symbol fop Min fBus/2048 0 2 4 1/2 1 1/2 1 tcyc - 30 tcyc - 30 15 15 0 25 -- -- -- -- 0 0 -- -- -- -- Max fBus/21 fBus/4 2048 -- -- -- -- -- 1024 tcyc -- -- -- -- -- 1 1 25 25 -- -- tcyc - 25 25 tcyc - 25 25 Unit Hz
1
D
tSPSCK
tcyc tcyc tSPSCK tcyc tSPSCK tcyc ns ns ns ns ns ns tcyc tcyc ns ns ns ns ns ns ns ns
2
D
tLead
3
D
tLag
4
D
tWSPSCK
5
D
tSU
6 7 8 9
D D D D
tHI ta tdis tv
10
D
tHO
11
D
tRI tRO tFI tFO
12
1
D
Max operating frequency limited to 8MHz when input filter disabled and high output drive strength enabled. Max operating frequency limited to 5MHz when input filter enabled and high output drive strength disabled.
MC9S08QE32 MCU Series Data Sheet, Rev. 1 22 Freescale Semiconductor
Electrical Characteristics
SS1 (OUTPUT) 2 SPSCK (CPOL = 0) (OUTPUT) SPSCK (CPOL = 1) (OUTPUT) 5 MISO (INPUT) 9 MOSI (OUTPUT) MSB OUT2 MSB IN2 6 BIT 6 . . . 1 9 BIT 6 . . . 1 LSB OUT LSB IN 10 1 4 4 12 11 3
NOTES: 1. SS output mode (DDS7 = 1, SSOE = 1). 2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure 17. SPI Master Timing (CPHA = 0)
SS(1) (OUTPUT) 1 2 SPSCK (CPOL = 0) (OUTPUT) 4 SPSCK (CPOL = 1) (OUTPUT) 5 MISO (INPUT) 9 MOSI (OUTPUT) PORT DATA MASTER MSB OUT(2) 6 MSB IN(2) BIT 6 . . . 1 10 BIT 6 . . . 1 MASTER LSB OUT PORT DATA LSB IN 4 11 12 12 11 3
NOTES: 1. SS output mode (DDS7 = 1, SSOE = 1). 2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure 18. SPI Master Timing (CPHA =1)
MC9S08QE32 MCU Series Data Sheet, Rev. 1 Freescale Semiconductor 23
Electrical Characteristics
SS (INPUT) 1 SPSCK (CPOL = 0) (INPUT) 2 SPSCK (CPOL = 1) (INPUT) 7 MISO (OUTPUT) SLAVE 5 MOSI (INPUT)
NOTE:
12
11
3
4
4
11
12 8
9 MSB OUT 6 MSB IN BIT 6 . . . 1 BIT 6 . . . 1
10
10 SEE NOTE
SLAVE LSB OUT
LSB IN
1. Not defined but normally MSB of character just received
Figure 19. SPI Slave Timing (CPHA = 0)
SS (INPUT) 1 2 SPSCK (CPOL = 0) (INPUT) 4 SPSCK (CPOL = 1) (INPUT) 9 MISO (OUTPUT) SEE NOTE 7 MOSI (INPUT) SLAVE 5 MSB IN MSB OUT 6 BIT 6 . . . 1 LSB IN 4 11 12 12 3 11
10 BIT 6 . . . 1 SLAVE LSB OUT
8
NOTE: 1. Not defined but normally LSB of character just received
Figure 20. SPI Slave Timing (CPHA = 1)
MC9S08QE32 MCU Series Data Sheet, Rev. 1 24 Freescale Semiconductor
Electrical Characteristics
3.11
C D P D P C P C
Analog Comparator (ACMP) Electricals
Table 14. Analog Comparator Electrical Specifications
Characteristic Symbol VDD IDDAC VAIN VAIO VH IALKG tAINIT 3.0 -- -- Min 1.8 -- VSS - 0.3 Typical -- 20 -- 20 9.0 -- -- Max 3.6 35 VDD 40 15.0 1.0 1.0 Unit V A V mV mV A s
Supply voltage Supply current (active) Analog input voltage Analog input offset voltage Analog comparator hysteresis Analog input leakage current Analog comparator initialization delay
3.12
C D
ADC Characteristics
Table 15. 12-bit ADC Operating Conditions
Conditions Absolute Delta to VDD (VDD-VDDAD)2 Symbol VDDAD VDDAD VSSAD VREFH VADIN CADIN RADIN 12 bit mode fADCK > 4 MHz fADCK < 4 MHz 10 bit mode fADCK > 4 MHz fADCK < 4 MHz 8 bit mode (all valid fADCK) RAS -- -- -- 0.4 fADCK 0.4 -- -- -- -- -- 5 10 10 8.0 4.0 MHz Min 1.8 -100 -100 1.8 VREFL -- -- Typical1 -- 0 0 VDDAD -- 4.5 5 Max 3.6 100 100 VDDAD VREFH 5.5 7 Unit V mV mV V V pF k Comment
Characteristic Supply voltage
D D D C C C
Ground voltage Ref Voltage High Input Voltage Input Capacitance Input Resistance Analog Source Resistance
Delta to
VSS (VSS-VSSAD)2
-- --
-- --
2 5 k External to MCU
D
ADC Conversion Clock Freq.
High Speed (ADLPC=0) Low Power (ADLPC=1)
Typical values assume VDDAD = 3.0 V, Temp = 25 C, fADCK=1.0 MHz unless otherwise state. Typical values are for reference only and are not tested in production. 2 DC potential difference.
1
MC9S08QE32 MCU Series Data Sheet, Rev. 1 Freescale Semiconductor 25
Electrical Characteristics
SIMPLIFIED INPUT PIN EQUIVALENT CIRCUIT ZAS RAS VADIN VAS Pad leakage due to input protection
ZADIN SIMPLIFIED CHANNEL SELECT CIRCUIT RADIN
ADC SAR ENGINE
+ -
+ -
CAS
RADIN INPUT PIN
RADIN
INPUT PIN
RADIN CADIN
INPUT PIN
Figure 21. ADC Input Impedance Equivalency Diagram Table 16. 12-bit ADC Characteristics (VREFH = VDDAD, VREFL = VSSAD)
C Characteristic Supply Current ADLPC=1 ADLSMP=1 ADCO=1 Supply Current ADLPC=1 ADLSMP=0 ADCO=1 Supply Current ADLPC=0 ADLSMP=1 ADCO=1 Supply Current ADLPC=0 ADLSMP=0 ADCO=1 ADC Asynchronous Clock Source High Speed (ADLPC=0) Low Power (ADLPC=1) fADACK Conditions Symbol Min Typical1 Max Unit Comment
T
IDDAD
--
120
--
A
T
IDDAD
--
202
--
A
T
IDDAD
--
288
--
A
P
IDDAD
--
0.532
1
mA
P P
2 1.25
3.3 2
5 MHz 3.3
tADACK = 1/fADACK
MC9S08QE32 MCU Series Data Sheet, Rev. 1 26 Freescale Semiconductor
Electrical Characteristics
Table 16. 12-bit ADC Characteristics (VREFH = VDDAD, VREFL = VSSAD)
C P C P Sample Time C T P T T P T T T T T P T T P T Full-Scale Error Zero-Scale Error Integral Non-Linearity Differential Non-Linearity Long Sample (ADLSMP=1) 12 bit mode 10 bit mode 8 bit mode 12 bit mode 10 bit mode3 8 bit mode3 12 bit mode 10 bit mode 8 bit mode 12 bit mode 10 bit mode 8 bit mode 12 bit mode 10 bit mode 8 bit mode 12 bit mode D Quantization Error 10 bit mode 8 bit mode 12 bit mode D Input Leakage Error 10 bit mode 8 bit mode D Temp Sensor Slope Temp Sensor Voltage -40C to 25C m 25C to 85C 25C VTEMP25 -- -- 1.769 701.2 -- -- mV EIL EQ EFS EZS INL DNL ETUE Characteristic Conversion Time (Including sample time) Conditions Short Sample (ADLSMP=0) Long Sample (ADLSMP=1) Short Sample (ADLSMP=0) tADS tADC Symbol Min -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Typical1 20 40 3.5 23.5 3.0 1 0.5 1.75 0.5 0.3 1.5 0.5 0.3 1.5 0.5 0.5 1.0 0.5 0.5 -1 to 0 -- -- 2 0.2 0.1 1.646 Max -- -- -- -- -- 2.5 1.0 -- 1.0 0.5 -- 1.0 0.5 -- 1.5 0.5 -- 1 0.5 -- 0.5 0.5 -- 4 1.2 -- mV/C LSB2 Pad leakage4 * RAS LSB2 LSB2 VADIN = VDDAD LSB2 VADIN = VSSAD LSB2 LSB2 LSB2 Includes quantization ADCK cycles Unit ADCK cycles Comment See ADC chapter in the QE32 Series MCU Reference Manual for conversion time variances
Total Unadjusted Error
D
1
Typical values assume VDDAD = 3.0 V, Temp = 25 C, fADCK=1.0 MHz unless otherwise stated. Typical values are for reference only and are not tested in production.
MC9S08QE32 MCU Series Data Sheet, Rev. 1 Freescale Semiconductor 27
Electrical Characteristics 1 LSB = (VREFH - VREFL)/2N Monotonicity and No-Missing-Codes guaranteed in 10 bit and 8 bit modes 4 Based on input pad leakage current. Refer to pad electricals.
2 3
3.13
Flash Specifications
This section provides details about program/erase times and program-erase endurance for flash memory. Program and erase operations do not require any special power sources other than the normal VDD supply. For more detailed information about program/erase operations, see MC9S08QE32 Series Reference Manual Chapter 4 Memory. Table 17. Flash Characteristics
C D D D D P P P P Characteristic Supply voltage for program/erase -40C to 85C Supply voltage for read operation Internal FCLK frequency1 location)(2) Symbol Vprog/erase VRead fFCLK tFcyc tprog tBurst tPage tMass RIDDBP RIDDPE -- -- 10,000 tD_ret 15 Min 1.8 1.8 150 5 Typical -- -- -- -- 9 4 4000 20,000 4 6 -- 100,000 100 -- -- -- -- -- Max 3.6 3.6 200 6.67 Unit V V kHz s tFcyc tFcyc tFcyc tFcyc mA mA
Internal FCLK period (1/FCLK) Byte program time (random Byte program time (burst Page erase Mass erase time2 time(2) current3 endurance4 current3 mode)(2)
Byte program Page erase C C
1 2
Program/erase TL to TH = -40C to 85C T = 25C Data retention5
cycles years
The frequency of this clock is controlled by software setting. These values are hardware state machine controlled. User code does not need to count cycles. This information is supplied for calculating approximate time to program and erase. 3 The program and erase currents are additional to the standard run I . These values are measured at room temperatures DD with VDD = 3.0 V, bus frequency = 4.0 MHz. 4 Typical endurance for flash was evaluated for this product family on the 9S12Dx64. For additional information on how Freescale defines typical endurance, please refer to Engineering Bulletin EB619, Typical Endurance for Nonvolatile Memory. 5 Typical data retention values are based on intrinsic capability of the technology measured at high temperature and de-rated to 25C using the Arrhenius equation. For additional information on how Freescale defines typical data retention, please refer to Engineering Bulletin EB618, Typical Data Retention for Nonvolatile Memory.
MC9S08QE32 MCU Series Data Sheet, Rev. 1 28 Freescale Semiconductor
Ordering Information
4
Ordering Information
This section contains ordering information for Device Numbering System Example of the device numbering system:
MC 9 S08 QE 32 Status (MC = Fully Qualified) Memory (9 = Flash-based) Core Family C XX
Package designator (see Table 18) Temperature range (C = -40C to 85C) Approximate flash size in kbytes
5
Package Information
Table 18. Package Descriptions
Pin Count 48 44 32 28 Package Type Quad Flat No-Leads Low Quad Flat Package Low Quad Flat Package Small Outline Integrated Circuit Abbreviation QFN LQFP LQFP SOIC Designator FT LD LC WL Case No. 1314 824D 873A 751F Document No. 98ARH99048A 98ASS23225W 98ASH70029A 98ASB42345B
5.1
Mechanical Drawings
The following pages are mechanical drawings for the packages described in Table 18. For the latest available drawings please visit our web site (http://www.freescale.com) and enter the package's document number into the keyword search box.
MC9S08QE32 MCU Series Data Sheet, Rev. 1 Freescale Semiconductor 29
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Document Number: MC9S08QE32 Rev. 1 6/2008

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